Semiconductor device attached to an exposed pad

ABSTRACT

The present disclosure provides for embodiments of packaged semiconductor devices. In one embodiment, a packaged semiconductor device for a die includes an exposed structure. The die has an active surface and a backside surface opposite the active surface. A first surface of the exposed structure is joined to die attach material, and the die attach material is further joined to the backside surface of the die. The exposed structure includes a plurality of openings through the exposed structure within a perimeter of the die, and the die is exposed through the plurality of openings.

BACKGROUND

1. Field

This disclosure relates generally to semiconductor devices, and morespecifically, to semiconductor devices attached to exposed pads.

2. Related Art

Some types of packaged semiconductor devices include a semiconductor diemounted on a lead frame. Lead frames, which include an exposed pad forattachment of the semiconductor die, are commonly manufactured byetching, stamping, and punching preformed sheets of metal such ascopper, copper alloys, and iron-nickel alloys into desired shapes. Acommon problem in attaching the semiconductor die to the exposed pad isdelamination. Another problem is that the material, commonly referencedas die attach, used to attach the semiconductor die to the exposed padmay crack and delaminate at the adjoining interfaces of the die attach.These problems have generally been approached by optimizing thematerials, materials' thicknesses, and the conditions, such astemperature, under which the materials are attached. Although theproblems have been reduced, they have not been completely solved,especially under all conditions.

Accordingly, there is a need for a further improvement in addressing oneor more of the problems noted above regarding the attachment of asemiconductor die to an exposed pad.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is illustrated by way of example and is notlimited by the accompanying figures, in which like references indicatesimilar elements. Elements in the figures are illustrated for simplicityand clarity and have not necessarily been drawn to scale.

FIG. 1 is a cross section of a semiconductor die;

FIG. 2 is a top view of an exposed pad of a lead frame.

FIG. 3 is a cross section of the integrated circuit die of FIG. 1 asattached to the exposed pad of FIG. 2;

FIG. 4 is a cross section of the integrated circuit die of FIG. 1 asattached to the exposed pad at a subsequent stage in processing to thatshown in FIG. 3;

FIG. 5 is a cross section of the integrated circuit die of FIG. 1 asattached to the exposed pad after being attached to a solderablesurface;

FIG. 6 is a cross section of a semiconductor die having a patterned backside;

FIG. 7 is a bottom view of the patterned backside of the semiconductordie;

FIG. 8 is a bottom view of a patterned backside of a leadframe;

FIG. 9 is a cross section of the semiconductor die of FIGS. 6 and 7 asattached to the lead frame of FIG. 8; and

FIG. 10 is a cross section of the semiconductor die and leadframe ofFIG. 9 attached to a solderable surface.

DETAILED DESCRIPTION

In one aspect, an exposed pad of a lead frame has openings which exposeportions of a backside of a semiconductor die. This allows for directaccess to the portions of the semiconductor die in forming thermallyconductive contacts to the semiconductor die. This is better understoodby reference to the FIGS. and the following written description.

Shown in FIG. 1 is a semiconductor die 10 having a top surface 11 whereactive circuitry is present and a backside 13. The active circuitryprovides functionality. Backside 13 is useful for contacting with heatdissipating elements.

Shown in FIG. 2 is an exposed pad 12, which is for contacting backside13, of a lead frame. Exposed pad 12 is a metal sheet 14 having holes 16,18, 20, 22, 24, 26 and 28 (16-28) in one row and holes 30, 32, 34, 36,38, 40, and 42 (30-42) in another row. Holes 16-28 and 30-42 passthrough metal sheet 14. These may be considered openings in which thedie is exposed through the openings. The openings are within a perimeterof die 10. Exposed pad 12 may be copper. The openings can occupysubstantial area. The area of the openings is related to the rigidityand strength of the material used for the exposed pad which is used tosupport semiconductor die 10.

Shown in FIG. 3 is a packaged die 50 having exposed pad 12 attached tobackside 13 of semiconductor die 10 with a die attach layer 52. Exposedpad 12 is shown in FIG. 3 in cross section 3-3 of FIG. 2. Exposed pad 12is formed prior to being attached to semiconductor die 10. Examples ofways exposed pad 12 may be formed include etching and stamping. Dieattach layer 52 is applied to exposed pad 12 which is then pressedagainst semiconductor die 10 to result in packaged die 50 as shown inFIG. 3. Additional packaging, which is not shown, may occur such asplastic encapsulation. Such additional packaging does not extend tocovering exposed pad 12. Backside surface 13 has a layer, such asaluminum, to which can be adhered a thermally conductive layer, such assolder. After attaching exposed pad 12, significant portions of thebackside of die 10 are still exposed. Thus, even after attaching exposedpad 12, which supports die 10, access to the backside of die 10 isavailable.

Shown in FIG. 4 is packaged die 50 after applying a highly thermallyconductive layer, such as solder, that at least partially fills openings16-28 of FIGS. 2 and 3. As shown, the highly thermally conductive layeroverfills openings 16-28 resulting in a thermally conductive fill 54 inopening 16, a thermally conductive fill 56 in opening 18, a thermallyconductive fill 58 in opening 20, a thermally conductive fill 60 inopening 22, a thermally conductive fill 62 in opening 24, a thermallyconductive fill 64 in opening 26, and a thermally conductive fill 66 inopening 28. Thermally conductive fills 54, 56, 58, 60, 62, 64, and 66(54-66) may be solder and thus may be characterized as solderstructures. Thermally conductive fills 54-66 are both joined to thesides of openings 16-28 and to semiconductor die 10 in openings 16-28.

Shown in FIG. 5 is an assembly 70 having packaged die 50 coupled to ametal solderable surface 74 which is coupled to a support 72 that may bea circuit board or other feature such as a metal pin, a printed circuitboard, a heat sink, an antenna, or even a motor vehicle. The attachmentutilizes additional conductive material that is combined with thermallyconductive fills (54-66) to result in a conductive fill layer 76 thatfills the region between semiconductor die 10 and metal solderablesurface 74. Some examples of a metal solderable surface include silver,gold, aluminum, tin, nickel-gold, and solder. Assembly 70 overcomes adiscovered problem that a die attach that extends across the entirelength of the backside of a semiconductor die can become detached andbecome a poor heat conductor. As shown for assembly 70, packaged die 50is supported by exposed pad 12. The openings in exposed pad 12 providefor direct contact of the conductive fill material to the die 10. Thisensures effective thermal conductivity from semiconductor die 10 tometal solderable surface 74. Conductive fill layer 76 functions as aheat spreader that may be sufficient. Support 72 may also function todissipate heat. Any problems with die attach layer 52 are bypassed bythe contact through openings 16-28 and further, because of openings16-28 which operate to relieve stress, there is less likelihood of dieattach layer 52 delaminating.

Shown in FIG. 6 is semiconductor die 80 having a top surface 81 wherethe active circuitry is present and a plurality of dimples 82, 84, 86,88, 90, and 92 (82-92) in an array on the backside have been formed.After forming dimples 82-92, which may be formed by a patterned etch, ametal deposition is performed resulting in a layer, which is solderable,being formed on the backside surface of die 80. This metallization stepensures that dimples 82-92 are solderable.

Shown in FIG. 7 is semiconductor die viewed toward the backside showingdimples 94, 96, 98, 100, 102, and 104 (94-104) in addition to dimples82-92. The view shown in FIG. 6 is the cross section taken at 6-6 ofFIG. 7. Dimples 82-92 and 94-104 may be formed by a patterned etch. Thisshows dimples 82-92 in one row and dimples 94-104 in a different row.

Shown in FIG. 8 is an exposed pad 108, which is for contacting thebackside of semiconductor die 80, of a lead frame. Exposed pad 108 is ametal sheet 110 having openings 112, 114, 116, 118, 120, and 122(112-122) in one row and openings 124, 126, 128, 130, 132, and 134(124-134) in another row. Openings 112-122 and 124-134 pass throughmetal sheet 110. Metal sheet 110 may be copper. Exposed pad 108 may bethe same as exposed pad 12 shown in FIG. 2. Openings 112-122 and 124-134are made to align to dimples 82-92 and 94-104.

Shown in FIG. 9 after attaching exposed pad 108 to the backside ofsemiconductor die 80 with centers of openings 112-122 substantiallyaligned to centers of dimples 82-92. Exposed pad 108 is attached tosemiconductor die 80 with a die attach 136. Although not shown in FIG.9, centers of openings 124-134 are similarly substantially aligned tocenters dimples 94-104.

Shown in FIG. 10 after filling openings 112-122 and dimples 82-92 with aconductive material 138, which may be solder, and attaching conductivematerial 138 to a metal solderable surface 142. This is readily achievedwith the alignment of openings 112-122 to dimples 82-92. Similar toassembly 70 of FIG. 5, solderable surface 142 is coupled to a support140 that may be a circuit board or other feature such as an electronicdevice that may even be a motor vehicle. In addition to the benefits, aspreviously described relative to FIG. 5, of exposed pad 108, which alsofunctions to support semiconductor die 80, dimples 82-92 operate toincrease the surface area of contact between conductive material 138 andsemiconductor die 80.

By now it is apparent that a semiconductor device has been described inwhich a packaged semiconductor device includes a die having an activesurface and a backside surface opposite the active surface. The packagedsemiconductor device further includes an exposed pad of a lead frame,wherein a first surface of the exposed pad is joined to die attachmaterial, the die attach material is further joined to the backsidesurface of the die, the exposed pad comprises a plurality of openingsthrough the exposed pad within a perimeter of the die, and the die isexposed through the plurality of openings. The packaged semiconductordevice may have a further characterization by which the die attachmaterial comprises a solder die attach material. The packagedsemiconductor device may have a further characterization by which thedie attach material is patterned with a second plurality of openingsthat are aligned to the plurality of openings. The packagedsemiconductor device may have a further characterization by which asolderable surface of the die is exposed through the plurality ofopenings. The packaged semiconductor device may have a furthercharacterization by which the die comprises a plurality of recesses onthe backside surface of the die, and the plurality of recesses arealigned with the plurality of openings. The packaged semiconductordevice may have a further characterization by which each of theplurality of recesses includes a solderable surface of the die, andsolderable surfaces of the plurality of recesses are exposed through theplurality of openings. The packaged semiconductor device may furtherinclude a plurality of solder structures joined to the die through theplurality of openings. The packaged semiconductor device may have afurther characterization by which the plurality of solder structures arefurther joined to sides of the plurality of openings. The packagedsemiconductor device may have a further characterization by which atleast one of the plurality of solder structures is further joined to atleast a portion of a second surface of the exposed pad, and the secondsurface of the exposed pad is opposite the first surface of the exposedpad. The packaged semiconductor device may have a furthercharacterization by which a second surface of the exposed pad is joinedto a solderable surface of a package mounting structure, and the secondsurface of the exposed pad is opposite the first surface of the exposedpad. The packaged semiconductor device may further include a solderlayer joined to the second surface of the exposed pad, wherein thesolder layer is further joined to the solderable surface of the packagemounting structure. The packaged semiconductor device may have a furthercharacterization by which the package mounting structure comprises oneof a metal pin, a printed circuit board, a heat sink, an antenna, and astructure having a solderable surface. The packaged semiconductor devicemay have a further characterization by which the die comprises one of asemiconductor die, a gauge, a sensor device, and a sensor die. Thepackaged semiconductor device may have a further characterization bywhich at least one of the plurality of recesses is located adjacent to aheat-producing area of the die. The packaged semiconductor device mayhave a further characterization by which each of the plurality ofrecesses has an opening into the backside surface of the die, and eachopening has a cross-sectional area bounded by at least one of apolygonal shape, a curved shape, and an amorphous shape.

Also described is a packaged semiconductor device for a die having anexposed structure, wherein the die has an active surface and a backsidesurface opposite the active surface, a first surface of the exposedstructure is joined to die attach material, the die attach material isfurther joined to the backside surface of the die, the exposed structurecomprises a plurality of openings through the exposed structure within aperimeter of the die, and the die is exposed through the plurality ofopenings. The packaged semiconductor device may have a furthercharacterization by which the exposed structure comprises one of a heatsink, an exposed pad of a lead frame, a metal pin, an antenna, and astructure having a solderable surface, and the die attach materialcomprises thermal interface material. The packaged semiconductor devicemay have a further characterization by which the thermal interfacematerial comprises a solder material, and the thermal interface materialis patterned with a second plurality of openings that are aligned to theplurality of openings. The packaged semiconductor device may have afurther characterization by which the die comprises a plurality ofrecesses on the backside surface of the die, and the plurality ofrecesses are aligned with the plurality of openings. The packagedsemiconductor device may have a further characterization by which one ormore solderable surfaces of the die are exposed through the plurality ofopenings, and a plurality of solder structures are joined to the diethrough the plurality of openings.

Although the disclosure is described herein with reference to specificembodiments, various modifications and changes can be made withoutdeparting from the scope of the present disclosure as set forth in theclaims below. Accordingly, the specification and figures are to beregarded in an illustrative rather than a restrictive sense, and allsuch modifications are intended to be included within the scope of thepresent disclosure. For example, the materials other than thosedescribed may be found to be effective. Any benefits, advantages, orsolutions to problems that are described herein with regard to specificembodiments are not intended to be construed as a critical, required, oressential feature or element of any or all the claims.

The term “coupled,” as used herein, is not intended to be limited to adirect coupling or a mechanical coupling.

Furthermore, the terms “a” or “an,” as used herein, are defined as oneor more than one. Also, the use of introductory phrases such as “atleast one” and “one or more” in the claims should not be construed toimply that the introduction of another claim element by the indefinitearticles “a” or “an” limits any particular claim containing suchintroduced claim element to disclosures containing only one suchelement, even when the same claim includes the introductory phrases “oneor more” or “at least one” and indefinite articles such as “a” or “an.”The same holds true for the use of definite articles.

Unless stated otherwise, terms such as “first” and “second” are used toarbitrarily distinguish between the elements such terms describe. Thus,these terms are not necessarily intended to indicate temporal or otherprioritization of such elements.

What is claimed is:
 1. A packaged semiconductor device comprising: a diehaving an active surface and a backside surface opposite the activesurface; and an exposed pad of a lead frame, wherein a first surface ofthe exposed pad is joined to die attach material, the die attachmaterial is further joined to the backside surface of the die, theexposed pad comprises a plurality of openings through the exposed padwithin a perimeter of the die, and the die is exposed through theplurality of openings.
 2. The packaged semiconductor device of claim 1,wherein the die attach material comprises a solder die attach material.3. The packaged semiconductor device of claim 1, wherein the die attachmaterial is patterned with a second plurality of openings that arealigned to the plurality of openings.
 4. The packaged semiconductordevice of claim 1, wherein a solderable surface of the die is exposedthrough the plurality of openings.
 5. The packaged semiconductor deviceof claim 1, wherein the die comprises a plurality of recesses on thebackside surface of the die, and the plurality of recesses are alignedwith the plurality of openings.
 6. The packaged semiconductor device ofclaim 5, wherein each of the plurality of recesses includes a solderablesurface of the die, and solderable surfaces of the plurality of recessesare exposed through the plurality of openings.
 7. The packagedsemiconductor device of claim 1, further comprising: a plurality ofsolder structures joined to the die through the plurality of openings.8. The packaged semiconductor device of claim 7, wherein the pluralityof solder structures are further joined to sides of the plurality ofopenings.
 9. The packaged semiconductor device of claim 7, wherein atleast one of the plurality of solder structures is further joined to atleast a portion of a second surface of the exposed pad, and the secondsurface of the exposed pad is opposite the first surface of the exposedpad.
 10. The packaged semiconductor device of claim 1, wherein a secondsurface of the exposed pad is joined to a solderable surface of apackage mounting structure, and the second surface of the exposed pad isopposite the first surface of the exposed pad.
 11. The packagedsemiconductor device of claim 10, further comprising: a solder layerjoined to the second surface of the exposed pad, wherein the solderlayer is further joined to the solderable surface of the packagemounting structure.
 12. The packaged semiconductor device of claim 10,wherein the package mounting structure comprises one of a metal pin, aprinted circuit board, a heat sink, an antenna, and a structure having asolderable surface.
 13. The packaged semiconductor device of claim 1,wherein the die comprises one of a semiconductor die, a gauge, a sensordevice, and a sensor die.
 14. The packaged semiconductor device of claim5, wherein at least one of the plurality of recesses is located adjacentto a heat-producing area of the die.
 15. The packaged semiconductordevice of claim 5, wherein each of the plurality of recesses has anopening into the backside surface of the die, and each opening has across-sectional area bounded by at least one of a polygonal shape, acurved shape, and an amorphous shape.
 16. A packaged semiconductordevice for a die comprising: an exposed structure, wherein the die hasan active surface and a backside surface opposite the active surface, afirst surface of the exposed structure is joined to die attach material,the die attach material is further joined to the backside surface of thedie, the exposed structure comprises a plurality of openings through theexposed structure within a perimeter of the die, and the die is exposedthrough the plurality of openings.
 17. The packaged semiconductor deviceof claim 16, wherein the exposed structure comprises one of a heat sink,an exposed pad of a lead frame, a metal pin, an antenna, and a structurehaving a solderable surface, and the die attach material comprisesthermal interface material.
 18. The packaged semiconductor device ofclaim 17, wherein the thermal interface material comprises a soldermaterial, and the thermal interface material is patterned with a secondplurality of openings that are aligned to the plurality of openings. 19.The packaged semiconductor device of claim 16, wherein the die comprisesa plurality of recesses on the backside surface of the die, and theplurality of recesses are aligned with the plurality of openings. 20.The packaged semiconductor device of claim 16, wherein one or moresolderable surfaces of the die are exposed through the plurality ofopenings, and a plurality of solder structures are joined to the diethrough the plurality of openings.